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SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos rev. 02 13 december 2004 product data 1. description the SC16C2552B is a two channel universal asynchronous receiver and transmitter (uart) used for serial data communications. its principal function is to convert parallel data into serial data, and vice versa. the uart can handle serial data rates up to 5 mbit/s. the SC16C2552B is pin compatible with the pc16552 and st16c2552. the SC16C2552B provides enhanced uart functions with 16 byte fifos, modem control interface, dma mode data transfer and concurrent writes to control registers of both channels. the dma mode data transfer is controlled by the fifo trigger levels and the rxrd y and txrd y signals. on-board status registers provide the user with error indications and operational status. system interrupts and modem control features may be tailored by software to meet speci?c user requirements. an internal loop-back capability allows on-board diagnostics. independent programmable baud rate generators are provided to select transmit and receive baud rates. the SC16C2552B operates at 5 v, 3.3 v and 2.5 v, and the industrial temperature range, and is available in a plastic plcc44 package. 2. features n industrial temperature range ( - 40 c to +85 c) n 5 v, 3.3 v and 2.5 v operation n pin-to-pin compatible to pc16c552, st16c2552 n up to 5 mbit/s data rate at 5 v and 3 v, and 3 mbit/s at 2.5 v n 16-byte transmit fifo n 16-byte receive fifo with error ?ags n independent transmit and receive uart control n four selectable receive fifo interrupt trigger levels; ?xed xmit fifo interrupt trigger level n modem control signals ( cts, r ts, dsr, dtr, ri, cd) n dma operation and dma monitoring via package i/o pins, txrd y/ rxrd y n uart internal register sections a and b may be written to concurrently n multi-function output allows more package functions with fewer i/o pins n programmable character lengths (5, 6, 7, 8), with even, odd, or no parity
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 2 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 3. ordering information 4. block diagram table 1: ordering information type number package name description version SC16C2552Bia44 plcc44 plastic leaded chip carrier; 44 leads sot187-2 fig 1. SC16C2552B block diagram. transmit fifo registers txa, txb receive shift register receive fifo registers rxa, rxb interconnect bus lines and control signals SC16C2552B transmit shift register modem control logic dtra , dtrb rtsa, rtsb mfa, mfb clock and baud rate generator ctsa , ctsb ria , rib cda , cdb dsra , dsrb xtal2 xtal1 data b u s and control logic d0Cd7 ior iow reset a0Ca2 cs chsel register select logic inta, intb txrdya , txrdyb rxrdya, rxrdyb interrupt control logic 002aaa487
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 3 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5. pinning information 5.1 pinning 5.2 pin description fig 2. plcc44 pin con?guration. SC16C2552Bia44 002aaa488 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 d4 d3 d2 d1 d0 txrdya v cc ria cda dsra ctsa cs mfb iow reset gnd rtsb ior rxb txb dtrb ctsb d5 d6 d7 a0 xtal1 gnd xtal2 a1 a2 chsel intb rxa txa dtra rtsa mfa inta v cc txrdyb rib cdb dsrb table 2: pin description symbol pin type description a0-a2 10, 14, 15 i register select. a0-a2 are used during read and write operations to select the uart register to read from or write to. chsel 16 i channel select. uart channel a or b is selected by the logical state of this pin when the cs is a logic 0. a logic 0 on chsel selects the uart channel b, while a logic 1 selects uart channel a. bit 0 of afr register can temporarily override chsel function, allowing user to write to both channel registers simultaneously with 1 write cycle. cs 18 i chip select (active-low). this function is selects channel a or b, in accordance with the logical state of the chsel pin. this allows data to be transferred between the user cpu and the SC16C2552B. d0-d7 2-9 i/o data bus (bi-directional). these pins are the 8-bit, 3-state data bus for transferring information to or from the controlling cpu. gnd 12, 22 i signal and power ground.
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 4 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. inta, intb 34, 17 o interrupt a, b (active-high). this function is associated with individual channel interrupts. interrupts are enabled in the interrupt enable register (ier). interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status ?ag is detected. ior 24 i read strobe (active-low). a logic 0 transition on this pin will load the contents of an internal register de?ned by address bits a0-a2 onto the SC16C2552B data bus (d0-d7) for access by external cpu. io w20i write strobe (active-low). a logic 0 transition on this pin will transfer the contents of the data bus (d0-d7) from the external cpu to an internal register that is de?ned by address bits a0-a2. mf a, mfb 35, 19 o multi-function a, b. this function is associated with an individual channel function, a or b. user programmable bits 1-2 of the alternate function register (afr), selects a signal function or output on these pins. op2 (interrupt enable), ba udout, and rxrd y are signal functions that may be selected by the afr. these signal functions are described as follows: op2. when op2 is selected, the mf pin is a logic 0 when mcr[3] is set to a logic 1. a logic 1 is the default signal condition that is available following a master reset or power-up. b a udout. when ba udout function is selected, the 16 baud rate clock output is available at this pin. rxrd y. rxrd y is primarily intended for monitoring dma mode 1 transfers for the receive data fifos. a logic 0 indicates there is receive data to read/unload, i.e., receive ready status with one or more rx characters available in the fifo/rhr. this pin is a logic 1 when the fifo/rhr is empty or when the programmed trigger level has not been reached. this signal can also be used for single mode transfers (dma mode 0). reset 21 i reset (active-high). a logic 1 on this pin will reset the internal registers and all the outputs. the uart transmitter output and the receiver input will be disabled during reset time. (see section 7.11 SC16C2552B external reset conditions for initialization details.) txrd y a, txrd yb 1, 32 o transmit ready a, b (active-low). these outputs provide the tx fifo/thr status for individual transmit channels (a-b). txrd yn is primarily intended for monitoring dma mode 1 transfers for the transmit data fifos. an individual channels txrd y a, txrd yb buffer ready status is indicated by logic 0, i.e., at least one location is empty and available in the fifo or thr. this pin goes to a logic 1 when there are no more empty locations in the fifo or thr. this signal can also be used for single mode transfers (dma mode 0). v cc 33, 44 i power supply input. xtal1 11 i crystal or external clock input. functions as a crystal input or as an external clock input. a crystal can be connected between this pin and xtal2 to form an internal oscillator circuit. alternatively, an external clock can be connected to this pin to provide custom data rates. (see section 6.5 programmable baud rate generator .) xtal2 13 o output of the crystal oscillator or buffered clock. (see also xtal1.) crystal oscillator output or buffered clock output. should be left open if an external clock is connected to xtal1. cd a, cdb 42, 30 i carrier detect (active-low). these inputs are associated with individual uart channels a through b. a logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. table 2: pin description continued symbol pin type description
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 5 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. ctsa, ctsb 40, 28 i clear to send (active-low). these inputs are associated with individual uart channels, a through b. a logic 0 on the cts pin indicates the modem or data set is ready to accept transmit data from the SC16C2552B. status can be tested by reading msr[4]. dsra, dsrb 41, 29 i data set ready (active-low). these inputs are associated with individual uart channels, a through b. a logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the uart. dtra, dtrb 37, 27 o data terminal ready (active-low). these outputs are associated with individual uart channels, a through b. a logic 0 on this pin indicates that the SC16C2552B is powered-on and ready. this pin can be controlled via the modem control register. writing a logic 1 to mcr[0] will set the dtr output to logic 0, enabling the modem. this pin will be a logic 1 after writing a logic 0 to mcr[0], or after a reset. ria, rib 43, 31 i ring indicator (active-low). these inputs are associated with individual uart channels, a through b. a logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. a logic 1 transition on this input pin will generate an interrupt if modem status interrupt is enabled. r tsa, r tsb 36, 23 o request to send (active-low). these outputs are associated with individual uart channels, a through b. a logic 0 on the r ts pin indicates the transmitter is ready to transmit data. writing a logic 1 in the modem control register mcr[1] will set this pin to a logic 0, indicating that the transmitter is ready to transmit data. after a reset this pin will be set to a logic 1. rxa, rxb 39, 25 i receive data a, b. these inputs are associated with individual serial channel data to the SC16C2552B receive input circuits, a-b. the rx signal will be a logic 1 during reset, idle (no data). during the local loop-back mode, the rx input pin is disabled and tx data is connected to the uart rx input, internally. txa, txb 38, 26 o transmit data a, b. these outputs are associated with individual serial transmit channel data from the SC16C2552B. the tx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. during the local loop-back mode, the tx output pin is disabled and tx data is internally connected to the uart rx input. table 2: pin description continued symbol pin type description
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 6 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. functional description the SC16C2552B provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. these functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character. data integrity is insured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the SC16C2552B is fabricated with an advanced cmos process. the SC16C2552B is an upward solution that provides a dual uart capability with 16 bytes of transmit and receive fifo memory, instead of none in the 16c450. the SC16C2552B is designed to work with high speed modems and shared network environments that require fast data processing time. increased performance is realized in the SC16C2552B by the transmit and receive fifos. this allows the external processor to handle more networking tasks within a given time. in addition, the four selectable receive fifo trigger interrupt levels are uniquely provided for maximum data throughput performance especially when operating in a multi-channel environment. the fifo memory greatly reduces the bandwidth requirement of the external controlling cpu, increases performance, and reduces power consumption. the SC16C2552B is capable of operation to 1.5 mbit/s with a 24 mhz crystal. with a crystal or external clock input of 7.3728 mhz, the user can select data rates up to 460.8 kbits/s. the rich feature set of the SC16C2552B is available through internal registers. selectable receive fifo trigger levels, selectable tx and rx baud rates, and modem interface controls are all standard features. 6.1 uart a-b functions the uart provides the user with the capability to bi-directionally transfer information between an external cpu, the SC16C2552B package, and an external serial device. a logic 0 on chip select pin cs, and a logic 1 on chsel allows the user to con?gure, send data, and/or receive data via uart channel a. a logic 0 on chip select pin cs and a logic 0 on chsel allows the user to con?gure, send data, and/or receive data via uart channel b. individual channel select functions are shown in ta b l e 3 . during a write mode cycle, the setting of afr[0] to a logic 1 will override the chsel selection and allow a simultaneous write to both uart channel sections. this functional capability allow the registers in both uart channels to be modi?ed concurrently, saving individual channel initialization time. caution should be considered, however, when using this capability. any in-process serial data transfer may be disrupted by changing an active channels mode. table 3: serial port selection chip select function cs = 1 none cs = 0 uart channel selected as follows: chsel = 1: uart channel a chsel = 0: uart channel b
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 7 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6.2 internal registers the SC16C2552B provides two sets of internal registers (a and b) consisting of 13 registers each for monitoring and controlling the functions of each channel of the uart. these registers are shown in ta b l e 4 . the uart registers function as data holding registers (thr/rhr), interrupt status and control registers (ier/isr), a fifo control register (fcr), line status and control registers (lcr/lsr), modem status and control registers (mcr/msr), programmable data rate (clock) control registers (dll/dlm), a user accessible scratchpad register (spr), and an alternate function register (afr). [1] the baud rate register and afr register sets are accessible only when cs is a logic 0 and lcr[7] is a logic 1 for the register set (a/b) being accessed. table 4: internal registers decoding a2 a1 a0 read mode write mode general register set (thr/rhr, ier/isr, mcr/msr, fcr, lsr, spr) 0 0 0 receive holding register transmit holding register 0 0 1 interrupt enable register interrupt enable register 0 1 0 interrupt status register fifo control register 0 1 1 line control register line control register 1 0 0 modem control register modem control register 1 0 1 line status register n/a 1 1 0 modem status register n/a 1 1 1 scratchpad register scratchpad register register set 2 (dll/dlm/afr) [1] 0 0 0 lsb of divisor latch lsb of divisor latch 0 0 1 msb of divisor latch msb of divisor latch 0 1 0 alternate function register alternate function register
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 8 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6.3 fifo operation the 16 byte transmit and receive data fifos are enabled by the fifo control register (fcr) bit 0. the user can set the receive trigger level via fcr bits 6-7, but not the transmit trigger level. the receiver fifo section includes a time-out function to ensure data is delivered to the external cpu. a time-out interrupt is generated whenever the receive holding register (rhr) has not been read following the loading of a character, or a receive trigger interrupt is generated when rx fifo level is equal to the program rx trigger value. 6.4 time-out interrupts the interrupts are enabled by ier[0-3]. care must be taken when handling these interrupts. following a reset if the transmitter interrupt is enabled, the SC16C2552B will issue an interrupt to indicate that transmit holding register is empty. the isr register provides the current singular highest priority interrupt only. it could be noted that a condition can exist where a higher priority interrupt may mask the lower priority interrupt(s). only after servicing the higher pending interrupt will the lower priority interrupt(s) be re?ected in the status register. servicing the interrupt without investigating further interrupt conditions can result in data errors. when two interrupt conditions have the same priority, it is important to service these interrupts correctly. receive data ready and receive time out have the same interrupt priority (when enabled by ier[0]). the receiver issues an interrupt after the number of characters have reached the programmed trigger level. in this case, the SC16C2552B fifo may hold more characters than the programmed trigger level. following the removal of a data byte, the user should re-check lsr[0] for additional characters. a receive time out will not occur if the receive fifo is empty. the time-out counter is reset at the center of each stop bit received or each time the receive holding register (rhr) is read. the actual time-out value is 4 character time. 6.5 programmable baud rate generator the SC16C2552B supports high speed modem technologies that have increased input data rates by employing data compression schemes. for example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. a 128.0 kbit/s isdn modem that supports data compression may need an input data rate of 460.8 kbit/s. a baud rate generator is provided for each uart channel, allowing independent tx/rx channel control. the programmable baud rate generator is capable of accepting an input clock up to 80 mhz, as required for supporting a 5 mbit/s data rate. the SC16C2552B can be con?gured for internal or external clock operation. for internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the xtal1 and xtal2 pins. alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates (see ta b l e 5 ). the generator divides the input 16 clock by any divisor from 1 to 2 16 - 1. the SC16C2552B divides the basic external clock by 16. the basic 16 clock provides table rates to support standard and custom applications using the same system
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 9 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. design. the rate table is con?gured via the dll and dlm internal register functions. customized baud rates can be achieved by selecting the proper divisor values for the msb and lsb sections of baud rate generator. programming the baud rate generator registers dlm (msb) and dll (lsb) provides a user capability for selecting the desired ?nal baud rate. the example in ta b l e 5 shows the selectable baud rate table available when using a 1.8432 mhz external clock input. fig 3. crystal oscillator connection. table 5: baud rate generator programming table using a 1.8432 mhz clock output baud rate output 16 clock divisor (decimal) user 16 clock divisor (hex) dlm program value (hex) dll program value (hex) 50 2304 900 09 00 75 1536 600 06 00 150 768 300 03 00 300 384 180 01 80 600 192 c0 00 c0 1200 96 60 00 60 2400 48 30 00 30 4800 24 18 00 18 7200 16 10 00 10 9600 12 0c 00 0c 19.2 k 6 06 00 06 38.4 k 3 03 00 03 57.6 k 2 02 00 02 115.2 k 1 01 00 01 002aaa125 y1 1.8432 mhz c1 22 pf c2 33 pf xtal1 xtal2
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 10 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6.6 dma operation the SC16C2552B fifo trigger level provides additional ?exibility to the user for block mode operation. lsr[5,6] provide an indication when the transmitter is empty or has an empty location(s). the user can optionally operate the transmit and receive fifos in the dma mode (fcr[3]). when the transmit and receive fifos are enabled and the dma mode is de-activated (dma mode 0), the SC16C2552B activates the interrupt output pin for each data transmit or receive operation. when dma mode is activated (dma mode 1), the user takes the advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the receive trigger level and the transmit fifo. in this mode, the SC16C2552B sets the interrupt output pin when characters in the transmit fifo is below 16, or the characters in the receive fifos are above the receive trigger level. 6.7 loop-back mode the internal loop-back capability allows on-board diagnostics. in the loop-back mode, the normal modem interface pins are disconnected and recon?gured for loop-back internally. mcr[0-3] register bits are used for controlling loop-back diagnostic testing. in the loop-back mode, int enable and mcr[2] in the mcr register (bits 2-3) control the modem ri and cd inputs, respectively. mcr signals dtr and r ts (bits 0-1) are used to control the modem dsr and cts inputs, respectively. the transmitter output (tx) and the receiver input (rx) are disconnected from their associated interface pins, and instead are connected together internally (see figure 4 ). the cts, dsr, cd, and ri are disconnected from their normal modem control inputs pins, and instead are connected internally to r ts, dtr, op2, and op1. loop-back test data is entered into the transmit holding register via the user data bus interface, d0-d7. the transmit uart serializes the data and passes the serial data to the receive uart via the internal loop-back connection. the receive uart converts the serial data back into parallel data that is then made available at the user data interface d0-d7. the user optionally compares the received data to the initial transmitted data for verifying error-free operation of the uart tx/rx circuits. in this mode, the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational. however, the interrupts can only be read using lower four bits of the modem status register (msr[0-3]) instead of the four modem status register bits 4-7. the interrupts are still controlled by the ier.
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 11 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 4. internal loop-back mode diagram. transmit fifo registers txa, txb receive shift register receive fifo registers rxa, rxb interconnect bus lines and control signals SC16C2552B transmit shift register modem control logic clock and baud rate generator xtal2 xtal1 data b u s and control logic d0Cd7 ior iow reset a0Ca2 cs register select logic inta, intb txrdya , txrdyb rxrdya , rxrdyb interrupt control logic 002aaa489 mcr[4] = 1 ctsa, ctsb rtsa, rtsb dtra, dtrb dsra, dsrb op1a, op1b cda, cdb ria, rib chsel op2a, op2b
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 12 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. register descriptions ta b l e 6 details the assigned bit functions for the SC16C2552B internal registers. the assigned bit functions are further de?ned in section 7.1 through section 7.11 . [1] the value shown in represents the registers initialized hex value; x = n/a. [2] the general register sets are accessible only when cs is a logic 0 and lcr[7] is a logic 0. [3] the baud rate register and afr register sets are accessible only when cs is a logic 0 and lcr[7] is a logic 1. set a is accessible when chsel is a logic 1, and set b is accessible when chsel is a logic 0. table 6: SC16C2552B internal registers a2 a1 a0 register default [1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 general register set [2] 0 0 0 rhr xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 thr xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 ier 00 0 0 0 0 modem status interrupt receive line status interrupt transmit holding register interrupt receive holding register 0 1 0 fcr 00 rcvr trigger (msb) rcvr trigger (lsb) 0 0 dma mode select xmit fifo reset rcvr fifo reset fifo enable 0 1 0 isr 01 fifos enabled fifos enabled 0 0 int priority bit 2 int priority bit 1 int priority bit 0 int status 0 1 1 lcr 00 divisor latch enable set break set parity even parity parity enable stop bits word length bit 1 word length bit 0 1 0 0 mcr 00 0 0 0 loop back op2 output control op1 r ts dtr 1 0 1 lsr 60 fifo data error thr and tsr empty thr empty break interrupt framing error parity error overrun error receive data ready 1 1 0 msr x0 cd ri dsr cts d cd d ri d dsr d cts 1 1 1 spr ff bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 special register set [3] 0 0 0 dll xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 dlm xx bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0 1 0 afr 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 13 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.1 transmit (thr) and receive (rhr) holding registers the serial transmitter section consists of an 8-bit transmit hold register (thr) and transmit shift register (tsr). the status of the thr is provided in the line status register (lsr). writing to the thr transfers the contents of the data bus (d7-d0) to the tsr and uart via the thr, providing that the thr is empty. the thr empty ?ag in the lsr[5] register will be set to a logic 1 when the transmitter is empty or when data is transferred to the tsr. the serial receive section also contains an 8-bit receive holding register (rhr) and a receive serial shift register (rsr). receive data is removed from the SC16C2552B and receive fifo by reading the rhr register. the receive section provides a mechanism to prevent false starts. on the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate. after 7- 1 2 clocks, the start bit time should be shifted to the center of the start bit. at this time the start bit is sampled, and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. receiver status codes will be posted in the lsr. 7.2 interrupt enable register (ier) the interrupt enable register (ier) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. these interrupts would normally be seen on the inta, intb output pins. table 7: interrupt enable register bits description bit symbol description 7-4 ier[7-4] not used; initialized to logic 0. 3 ier[3] modem status interrupt. this interrupt will be issued whenever there is a modem status change as re?ected in msr[0-3]. logic 0 = disable the modem status register interrupt (normal default condition). logic 1 = enable the modem status register interrupt. 2 ier[2] receive line status interrupt. this interrupt will be issued whenever a receive data error condition exists as re?ected in lsr[1-4]. logic 0 = disable the receiver line status interrupt (normal default condition). logic 1 = enable the receiver line status interrupt. 1 ier[1] transmit holding register interrupt. in the 16c450 mode, this interrupt will be issued whenever the thr is empty, and is associated with lsr[5]. in the fifo modes, this interrupt will be issued whenever the fifo and thr are empty. logic 0 = disable the transmit holding register empty (txrdy) interrupt (normal default condition). logic 1 = enable the txrdy (isr level 3) interrupt.
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 14 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.2.1 ier versus transmit/receive fifo interrupt mode operation when the receive fifo (fcr[0] = logic 1), and receive interrupts (ier[0] = logic 1) are enabled, the receive interrupts and register status will re?ect the following: ? the receive rxrdy interrupt (level 2 isr interrupt) is issued to the external cpu when the receive fifo has reached the programmed trigger level. it will be cleared when the receive fifo drops below the programmed trigger level. ? receive fifo status will also be re?ected in the user accessible isr register when the receive fifo trigger level is reached. both the isr register receive status bit and the interrupt will be cleared when the fifo drops below the trigger level. ? the receive data ready bit (lsr[0]) is set as soon as a character is transferred from the shift register (rsr) to the receive fifo. it is reset when the fifo is empty. ? when the transmit fifo and interrupts are enabled, an interrupt is generated when the transmit fifo is empty due to the unloading of the data by the tsr and uart for transmission via the transmission media. the interrupt is cleared either by reading the isr register, or by loading the thr with new data characters. 7.2.2 ier versus receive/transmit fifo polled mode operation when fcr[0] = logic 1, resetting ier[0-3] enables the SC16C2552B in the fifo polled mode of operation. in this mode, interrupts are not generated and the user must poll the lsr register for tx and/or rx data status. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ? lsr[0] will be a logic 1 as long as there is one byte in the receive fifo. ? lsr[1-4] will provide the type of receive errors, or a receive break, if encountered. ? lsr[5] will indicate when the transmit fifo is empty. ? lsr[6] will indicate when both the transmit fifo and transmit shift register are empty. ? lsr[7] will show if any fifo data errors occurred. 0 ier[0] receive holding register. in the 16c450 mode, this interrupt will be issued when the rhr has data, or is cleared when the rhr is empty. in the fifo mode, this interrupt will be issued when the fifo has reached the programmed trigger level or is cleared when the fifo drops below the trigger level. logic 0 = disable the receiver ready (isr level 2, rxrdy) interrupt (normal default condition). logic 1 = enable the rxrdy (isr level 2) interrupt. table 7: interrupt enable register bits description continued bit symbol description
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 15 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.3 fifo control register (fcr) this register is used to enable the fifos, clear the fifos, set the receive fifo trigger levels, and select the dma mode. 7.3.1 dma mode mode 0 (fcr bit 3 = 0): set and enable the interrupt for each single transmit or receive operation, and is similar to the 16c450 mode. transmit ready ( txrd y) will go to a logic 0 whenever an empty transmit space is available in the transmit holding register (thr). receive ready ( rxrd y) at the mf pin will go to a logic 0 whenever the receive holding register (rhr) is loaded with a character and the mf register is set to the rxrdy mode. mode 1 (fcr bit 3 = 1): set and enable the interrupt in a block mode operation. the transmit interrupt is set when the transmit fifo has at least one empty location. txrd y remains a logic 0 as long as one empty fifo location is available. the receive interrupt is set when the receive fifo ?lls to the programmed trigger level. however, the fifo continues to ?ll regardless of the programmed level until the fifo is full. rxrd y at the mf pin remains a logic 0 as long as the fifo ?ll level is above the programmed trigger level, and the mf register is set to the rxrdy mode. 7.3.2 fifo mode table 8: fifo control register bits description bit symbol description 7-6 fcr[7-6] rcvr trigger. these bits are used to set the trigger level for the receive fifo interrupt. an interrupt is generated when the number of characters in the fifo equals the programmed trigger level. however, the fifo will continue to be loaded until it is full. refer to ta b l e 9 . 5-4 fcr[5-4] not used; initialized to logic 0. 3 fcr[3] dma mode select. logic 0 = set dma mode 0 (normal default condition). logic 1 = set dma mode 1 transmit operation in mode 0: when the SC16C2552B is in the 16c450 mode (fifos disabled; fcr[0] = logic 0) or in the fifo mode (fifos enabled; fcr[0] = logic 1; fcr[3] = logic 0), and when there are no characters in the transmit fifo or transmit holding register, the txrd y pin will be a logic 0. once active, the txrd y pin will go to a logic 1 after the ?rst character is loaded into the transmit holding register. receive operation in mode 0: when the SC16C2552B is in 16c450 mode, or in the fifo mode (fcr[0] = logic 1; fcr[3] = logic 0) and there is at least one character in the receive fifo, the rxrd y signal at the mf pin will be a logic 0. once active, the rxrd y signal at the mf pin will go to a logic 1 when there are no more characters in the receiver. note: the afr register must be set to the rxrdy mode prior to any possible reading of the rxrd y signal.
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 16 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 3 (continued) transmit operation in mode 1: when the SC16C2552B is in fifo mode (fcr[0] = logic 1; fcr[3] = logic 1), the txrd y pin will be a logic 1 when the transmit fifo is completely full. it will be a logic 0 if one or more fifo locations are empty. receive operation in mode 1: when the SC16C2552B is in fifo mode (fcr[0] = logic 1; fcr[3] = logic 1) and the trigger level has been reached, or a receive time-out has occurred, the rxrd y signal at the mf pin will go to a logic 0. once activated, it will go to a logic 1 after there are no more characters in the fifo. note: the afr register must be set to the rxrdy mode prior to any possible reading of the rxrd y signal. 2 fcr[2] xmit fifo reset. logic 0 = no fifo transmit reset (normal default condition). logic 1 = clears the contents of the transmit fifo and resets the fifo counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. 1 fcr[1] rcvr fifo reset. logic 0 = no fifo receive reset (normal default condition). logic 1 = clears the contents of the receive fifo and resets the fifo counter logic (the receive shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. 0 fcr[0] fifos enabled. logic 0 = disable the transmit and receive fifo (normal default condition). logic 1 = enable the transmit and receive fifo. this bit must be a 1 when other fcr bits are written to, or they will not be programmed. table 9: rcvr trigger levels fcr[7] fcr[6] rx fifo trigger level 0001 0104 1008 1114 table 8: fifo control register bits description continued bit symbol description
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 17 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.4 interrupt status register (isr) the SC16C2552B provides four levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with four interrupt status bits. performing a read cycle on the isr will provide the user with the highest pending interrupt level to be serviced. no other interrupts are acknowledged until the pending interrupt is serviced. whenever the interrupt status register is read, the interrupt status is cleared. however, it should be noted that only the current pending interrupt is cleared by the read. a lower level interrupt may be seen after re-reading the interrupt status bits. table 10 interrupt source shows the data values (bits 0-3) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. table 10: interrupt source priority level isr[3] isr[2] isr[1] isr[0] source of the interrupt 1 0 1 1 0 lsr (receiver line status register) 2 0 1 0 0 rxrdy (received data ready) 2 1 1 0 0 rxrdy (receive data time-out) 3 0 0 1 0 txrdy (transmitter holding register empty) 4 0 0 0 0 msr (modem status register) table 11: interrupt status register bits description bit symbol description 7-6 isr[7-6] fifos enabled. these bits are set to a logic 0 when the fifos are not being used in the 16c450 mode. they are set to a logic 1 when the fifos are enabled in the SC16C2552B mode. logic 0 or cleared = default condition. 5-4 isr[5-4] not used; initialized to a logic 0. 3-1 isr[3-1] int priority bits. these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see ta b l e 1 0 ). 0 isr[0] int status. logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. logic 1 = no interrupt pending (normal default condition).
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 18 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.5 line control register (lcr) the line control register is used to specify the asynchronous data communication format. the word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. table 12: line control register bits description bit symbol description 7 lcr[7] divisor latch enable. the internal baud rate counter latch and enhance feature mode enable. logic 0 = divisor latch disabled (normal default condition). logic 1 = divisor latch enabled. 6 lcr[6] set break. when enabled, the break control bit causes a break condition to be transmitted (the tx output is forced to a logic 0 state). this condition exists until disabled by setting lcr[6] to a logic 0. logic 0 = no tx break condition (normal default condition) logic 1 = forces the transmitter output (tx) to a logic 0 for alerting the remote receiver to a line break condition. 5-3 lcr[5-3] programs the parity conditions (see ta b l e 1 3 ). 2 lcr[2] stop bits. the length of stop bit is speci?ed by this bit in conjunction with the programmed word length (see ta b l e 1 4 ). logic 0 or cleared = default condition. 1-0 lcr[1-0] word length bits 1, 0. these two bits specify the word length to be transmitted or received (see ta b l e 1 5 ). logic 0 or cleared = default condition. table 13: lcr[5] parity selection lcr[5] lcr[4] lcr[3] parity selection x x 0 no parity x 0 1 odd parity 0 1 1 even parity 001f orce parity 1 111f orced parity 0 table 14: lcr[2] stop bit length lcr[2] word length stop bit length (bit times) 0 5, 6, 7, 8 1 15 1- 1 2 1 6, 7, 8 2 table 15: lcr[1-0] word length lcr[1] lcr[0] word length 005 016 107 118
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 19 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.6 modem control register (mcr) this register controls the interface with the modem or a peripheral device. table 16: modem control register bits description bit symbol description 7-5 mcr[7-5] not used; initialized to a logic 0. 4 mcr[4] loop-back. enable the local loop-back mode (diagnostics). in this mode the transmitter output tx and the receiver input rx, cts, dsr, cd, and ri are disconnected from the SC16C2552B i/o pins. internally the modem data and control pins are connected into a loop-back data con?guration (see figure 4 ). in this mode, the receiver and transmitter interrupts remain fully operational. the modem control interrupts are also operational, but the interrupts sources are switched to the lower four bits of the modem control. interrupts continue to be controlled by the ier register. logic 0 = disable loop-back mode (normal default condition). logic 1 = enable local loop-back mode (diagnostics). 3 mcr[3] op2. used to control the modem cd signal in the loop-back mode. logic 0 = sets op2 to a logic 1 (normal default condition). in the loop-back mode, sets cd internally to a logic 1. logic 1 = sets op2 to a logic 0. in the loop-back mode, sets cd internally to a logic 0. 2 mcr[2] op1. this bit is used in the loop-back mode only. in the loop-back mode, this bit is used to write the state of the modem ri interface signal. 1 mcr[1] r ts logic 0 = force r ts output to a logic 1 (normal default condition). logi c1=f orce r ts output to a logic 0. 0 mcr[0] dtr logic 0 = force dtr output to a logic 1 (normal default condition). logic 1 = force dtr output to a logic 0.
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 20 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.7 line status register (lsr) this register provides the status of data transfers between the SC16C2552B and the cpu. table 17: line status register bits description bit symbol description 7 lsr[7] fifo data error. logic 0 = no error (normal default condition). logic 1 = at least one parity error, framing error or break indication is in the current fifo data. this bit is cleared when rhr register is read. 6 lsr[6] thr and tsr empty. this bit is the transmit empty indicator. this bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. it is reset to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode, this bit is set to 1 whenever the transmit fifo and transmit shift register are both empty. 5 lsr[5] thr empty. this bit is the transmit holding register empty indicator. this bit indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to cpu when the thr interrupt enable is set. the thr bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. the bit is reset to a logic 0 concurrently with the loading of the transmitter holding register by the cpu. in the fifo mode, this bit is set when the transmit fifo is empty; it is cleared when at least 1 byte is written to the transmit fifo. 4 lsr[4] break interrupt. logic 0 = no break condition (normal default condition). logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). in the fifo mode, only one break character is loaded into the fifo. 3 lsr[3] framing error. logic 0 = no framing error (normal default condition). logic 1 = framing error. the receive character did not have a valid stop bit(s). in the fifo mode, this error is associated with the character at the top of the fifo. 2 lsr[2] parity error. logic 0 = no parity error (normal default condition). logic 1 = parity error. the receive character does not have correct parity information and is suspect. in the fifo mode, this error is associated with the character at the top of the fifo. 1 lsr[1] overrun error. logic 0 = no overrun error (normal default condition). logi c1=overrun error. a data overrun error occurred in the receive shift register. this happens when additional data arrives while the fifo is full. in this case, the previous data in the shift register is overwritten. note that under this condition, the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error.
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 21 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.8 modem status register (msr) this register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C2552B is connected. four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a control input from the modem changes state. these bits are set to a logic 0 whenever the cpu reads this register. [1] whenever any msr bit 0-3 is set to logic 1, a modem status interrupt will be generated. 0 lsr[0] receive data ready. logic 0 = no data in receive holding register or fifo (normal default condition). logic 1 = data has been received and is saved in the receive holding register or fifo. table 17: line status register bits description continued bit symbol description table 18: modem status register bits description bit symbol description 7 msr[7] carrier detect, cd. during normal operation, this bit is the complement of the cd input. reading this bit in the loop-back mode produces the state of mcr[3] ( op a/opb). 6 msr[6] ring indicator, ri. during normal operation, this bit is the complement of the ri input. reading this bit in the loop-back mode produces the state of mcr[2] ( op1). 5 msr[5] data set ready, dsr. during normal operation, this bit is the complement of the dsr input. during the loop-back mode, this bit is equivalent to mcr[0] ( dtr). 4 msr[4] clear to send, cts. during normal operation, this bit is the complement of the cts input. during the loop-back mode, this bit is equivalent to mcr[1] ( r ts). 3 msr[3] d cd [1] logic 0 = no cd change (normal default condition). logi c1=the cd input to the SC16C2552B has changed state since the last time it was read. a modem status interrupt will be generated. 2 msr[2] d ri [1] logic 0 = no ri change (normal default condition). logi c1=the ri input to the SC16C2552B has changed from a logic 0 to a logic 1. a modem status interrupt will be generated. 1 msr[1] d dsr [1] logic 0 = no dsr change (normal default condition). logi c1=the dsr input to the SC16C2552B has changed state since the last time it was read. a modem status interrupt will be generated. 0 msr[0] d cts [1] logic 0 = no cts change (normal default condition). logic 1 = the cts input to the SC16C2552B has changed state since the last time it was read. a modem status interrupt will be generated.
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 22 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.9 scratchpad register (spr) the SC16C2552B provides a temporary data register to store 8 bits of user information. 7.10 alternate function register (afr) this is a read/write register used to select speci?c modes of mf operation and to allow both uart registers sets to be written concurrently. table 19: alternate function register bits description bit symbol description 7-3 afr[7-3] not used. all are initialized to logic 0. 2-1 afr[2-1] selects a signal function for output on the mf a, mfb pins. these signal functions are described as: op2 (interrupt enable), ba udout, or rxrd y. only one signal function can be selected at a time. see ta b l e 2 0 . 0 afr[0] when this bit is set, cpu can write concurrently to the same register in both uarts. this function is intended to reduce the dual uart initialization time. it can be used by cpu when both channels are initialized to the same state. the external cpu can set or clear this bit by accessing either register set. when this bit is set, the channel select pin still selects the channel to be accessed during read operation. setting or clearing this bit has no effect on read operations. the user should ensure that lcr[7] of both channels are in the same state before executing a concurrent write to the registers at address 0, 1, or 2. logic 0 = no concurrent write (normal default condition). logic 1 = register set a and b are written concurrently with a single external cpu i/o write operation. table 20: mf a, mfb function selection afr[2] afr[1] mf function 00 op2 01 ba udout 10 rxrd y 1 1 reserved
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 23 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.11 SC16C2552B external reset conditions 8. limiting values table 21: reset state for registers register reset state ier ier[7-0] = 0 isr isr[7-1] = 0; isr[0] = 1 lcr lcr[7-0] = 0 mcr mcr[7-0] = 0 lsr lsr[7] = 0; lsr[6-5] = 1; lsr[4-0] = 0 msr msr[7-4] = input signals; msr[3-0] = 0 fcr fcr[7-0] = 0 afr afr[7-0] = 0 table 22: reset state for outputs output reset state txa, txb high op2a, op2b high r tsa, r tsb high dtra, dtrb high inta, intb low txrd y a, txrd yb low table 23: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage - 7 v v n voltage at any pin gnd - 0.3 v cc + 0.3 v t amb operating temperature - 40 +85 c t stg storage temperature - 65 +150 c p tot(pack) total power dissipation per package - 500 mw
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 24 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9. static characteristics [1] except x 2 , v ol = 1 v typical. table 24: dc electrical characteristics t amb = - 40 c to +85 c; v cc = 2.5 v, 3.3 v or 5.0 v 10%, unless otherwise speci?ed. symbol parameter conditions 2.5 v 3.3 v 5.0 v unit min max min max min max v il(ck) low-level clock input voltage - 0.3 0.45 - 0.3 0.6 - 0.5 0.6 v v ih(ck) high-level clock input voltage 1.8 v cc 2.4 v cc 3.0 v cc v v il low-level input voltage (except x1 clock) - 0.3 0.65 - 0.3 0.8 - 0.5 0.8 v v ih high-level input voltage (except x1 clock) 1.6 - 2.0 - 2.2 - v v ol low-level output voltage on all outputs [1] i ol =5ma (databus) -----0.4v i ol =4ma (other outputs) ---0.4--v i ol =2ma (databus) -0.4----v i ol = 1.6 ma (other outputs) -0.4----v v oh high-level output voltage i oh = - 5ma (databus) ----2.4-v i oh = - 1ma (other outputs) --2.0---v i oh = - 800 m a (data bus) 1.85 -----v i oh = - 400 m a (other outputs) 1.85 -----v i lil low-level input leakage current - 10 - 10 - 10 m a i cl clock leakage - 30 - 30 - 30 m a i cc supply current f = 5 mhz - 3.5 - 4.5 - 4.5 ma c i input capacitance - 5 - 5 - 5 pf
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 25 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. dynamic characteristics [1] applies to external clock, crystal oscillator max 24 mhz. table 25: ac electrical characteristics t amb = - 40 c to +85 c; v cc = 2.5 v, 3.3 v or 5.0 v 10%, unless otherwise speci?ed. symbol parameter conditions 2.5 v 3.3 v 5.0 v unit min max min max min max t 1w , t 2w clock pulse duration 10 - 6 - 6 - ns t 3w clock frequency [1] - 48 - 80 80 mhz t 6s address set-up time 0 - 0 - 0 - ns t 6h address hold time 0 - 0 - 0 - ns t 7d ior delay from chip select 10 - 10 - 10 - ns t 7w ior strobe width 25 pf load 77 - 26 - 23 - ns t 7h chip select hold time from ior 0 - 0 - 0 - ns t 9d read cycle delay 25 pf load 20 - 20 - 20 - ns t 12d delay from ior to data 25 pf load - 77 - 26 - 23 ns t 12h data disable time 25 pf load - 15 - 15 - 15 ns t 13d io w delay from chip select 10 - 10 - 10 - ns t 13w io w strobe width 20 - 20 - 15 - ns t 13h chip select hold time from io w 0-0-0-ns t 15d write cycle delay 25 - 25 - 20 - ns t 16s data set-up time 20 - 20 - 15 - ns t 16h data hold time 15 - 5 - 5 - ns t 17d delay from io w to output 25 pf load - 100 - 33 - 29 ns t 18d delay to set interrupt from modem input 25 pf load - 100 - 24 - 23 ns t 19d delay to reset interrupt from ior 25 pf load - 100 - 24 - 23 ns t 20d delay from stop to set interrupt - 1 - 1 - 1 r clk t 21d delay from ior to reset interrupt 25 pf load - 100 - 29 - 28 ns t 22d delay from start to set interrupt - 100 - 45 - 40 ns t 23d delay from io w to transmit start 8 24 8 24 8 24 r clk t 24d delay from io w to reset interrupt - 100 - 45 - 40 ns t 25d delay from stop to set rxrd y -1-1-1r clk t 26d delay from ior to reset rxrd y - 100 - 45 - 40 ns t 27d delay from io w to set txrd y - 100 - 45 - 40 ns t 28d delay from start to reset txrd y -8-8-8r clk t reset reset pulse width 200 - 40 - 40 - ns n baud rate divisor 1 2 16 - 11 2 16 - 11 2 16 - 1r clk
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 26 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.1 timing diagrams fig 5. general write timing. data active active valid address 002aaa128 t 6s t 13h t 13d t 13w t 15d t 16s t 16h a0Ca2 cs iow d0Cd7 chsel t 6h fig 6. general read timing. data active active valid address 002aaa127 t 6s t 7h t 7d t 7w t 9d t 12d t 12h a0Ca2 cs ior d0Cd7 chsel t 6h
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 27 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 7. modem input/output timing. t 17d change of state t 18d t 18d t 19d 002aaa352 t 18d change of state change of state change of state active active active active active active active change of state rts dtr iow cd cts dsr int ior ri fig 8. external clock timing. external clock 002aaa112 t 3w t 2w t 1w
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 28 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 9. receive timing. d0 d1 d2 d3 d4 d5 d6 d7 active active 16 baud rate clock 002aaa113 rx int ior t 21d t 20d 5 data bits 6 data bits 7 data bits stop bit parity bit start bit data bits (0 to 7) next data start bit fig 10. receive ready timing in non-fifo mode. d0 d1 d2 d3 d4 d5 d6 d7 active data ready active 002aaa578 t 26d next data start bit stop bit parity bit start bit t 25d rx rxrdy ior data bits (5C8)
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 29 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 11. receive ready timing in fifo mode. d0 d1 d2 d3 d4 d5 d6 d7 active data ready active 002aaa579 t 26d stop bit parity bit start bit t 25d rx rxrdy ior data bits (5C8) first byte that reaches the trigger level fig 12. transmit timing. active transmitter ready active 16 baud rate clock 002aaa116 t 24d int iow active d0 d1 d2 d3 d4 d5 d6 d7 tx 5 data bits 6 data bits 7 data bits stop bit parity bit start bit data bits (0 to 7) next data start bit t 22d t 23d
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 30 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 13. transmit ready timing in non-fifo mode. d0 d1 d2 d3 d4 d5 d6 d7 transmitter not ready 002aaa580 next data start bit stop bit parity bit start bit t 27d tx txrdy iow data bits (5-8) active d0-d7 byte #1 active transmitter ready t 28d
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 31 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 14. transmit ready timing in fifo mode (dma mode 1). d0 d1 d2 d3 d4 d5 d6 d7 fifo full 002aaa581 stop bit parity bit start bit t 27d tx txrdy iow data bits (5-8) active d0Cd7 byte #16 5 data bits 6 data bits 7 data bits t 28d
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 32 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. package outline fig 15. plcc44 package outline (sot187-2). unit a a 1 min. a 4 max. b p ey w v b references outline version european projection issue date iec jedec jeita mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 16.66 16.51 1.27 17.65 17.40 2.16 45 o 0.18 0.1 0.18 dimensions (mm dimensions are derived from the original inch dimensions) note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. sot187-2 d (1) e (1) 16.66 16.51 h d h e 17.65 17.40 z d (1) max. z e (1) max. 2.16 b 1 0.81 0.66 k 1.22 1.07 0.180 0.165 0.02 0.12 a 3 0.25 0.01 0.656 0.650 0.05 0.695 0.685 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 0.656 0.650 0.695 0.685 e d e e 16.00 14.99 0.63 0.59 16.00 14.99 0.63 0.59 0.085 0.032 0.026 0.048 0.042 29 39 44 1 6 717 28 18 40 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k x y e e b d h e e e h v m b d z d a z e e v m a pin 1 index 112e10 ms-018 edr-7319 0 5 10 mm scale 99-12-27 01-11-14 inches plcc44: plastic leaded chip carrier; 44 leads sot187-2 d e
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 33 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. soldering 12.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. in these situations re?ow soldering is recommended. 12.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 12.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 34 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 12.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 12.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 26: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5][6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos product data rev. 02 13 december 2004 35 of 37 9397 750 14442 ? koninklijke philips electronics n.v. 2004. all rights reserved. [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vsop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 13. revision history table 27: revision history rev date cpcn description 02 20041213 - product data (9397 750 14442) modi?cations: ? there is no modi?cation to the data sheet. however, reader is advised to refer to an10333 (rev. 02) sc16cxxxb baud rate deviation tolerance (9397 750 14411) that was released together with this revision. 01 20040330 - product data (9397 750 11966)
9397 750 14442 philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 02 13 december 2004 36 of 37 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 14. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 15. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 16. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004. printed in the u.s.a. all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 13 december 2004 document order number: 9397 750 14442 contents philips semiconductors SC16C2552B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 functional description . . . . . . . . . . . . . . . . . . . 6 6.1 uart a-b functions . . . . . . . . . . . . . . . . . . . . . 6 6.2 internal registers. . . . . . . . . . . . . . . . . . . . . . . . 7 6.3 fifo operation . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4 time-out interrupts . . . . . . . . . . . . . . . . . . . . . . 8 6.5 programmable baud rate generator . . . . . . . . . 8 6.6 dma operation . . . . . . . . . . . . . . . . . . . . . . . . 10 6.7 loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 10 7 register descriptions . . . . . . . . . . . . . . . . . . . 12 7.1 transmit (thr) and receive (rhr) holding registers . . . . . . . . . . . . . . . . . . . . . 13 7.2 interrupt enable register (ier) . . . . . . . . . . . 13 7.2.1 ier versus transmit/receive fifo interrupt mode operation . . . . . . . . . . . . . . . . . . . . . . . 14 7.2.2 ier versus receive/transmit fifo polled mode operation . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 fifo control register (fcr) . . . . . . . . . . . . . 15 7.3.1 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 interrupt status register (isr) . . . . . . . . . . . . 17 7.5 line control register (lcr) . . . . . . . . . . . . . . 18 7.6 modem control register (mcr) . . . . . . . . . . . 19 7.7 line status register (lsr) . . . . . . . . . . . . . . . 20 7.8 modem status register (msr). . . . . . . . . . . . 21 7.9 scratchpad register (spr) . . . . . . . . . . . . . . 22 7.10 alternate function register (afr) . . . . . . . . . 22 7.11 SC16C2552B external reset conditions . . . . . 23 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 23 9 static characteristics . . . . . . . . . . . . . . . . . . . 24 10 dynamic characteristics . . . . . . . . . . . . . . . . . 25 10.1 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 26 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 32 12 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12.2 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 33 12.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 33 12.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 34 12.5 package related soldering information . . . . . . 34 13 revision history . . . . . . . . . . . . . . . . . . . . . . . 35 14 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 36 15 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 16 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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